When power consumption of an integrated circuit such as an LSI (Large Scale Integrated circuit) or the like is obtained in a design phase, the following processes have been carried out.
Signal transition pattern information, obtained by executing a logic simulation process for an integrated circuit, of an input/output signal terminal of each of cells that configure the integrated circuit, cell power information, obtained by executing a circuit simulation process (such as SPICE: Simulation Program with Integrated Circuit Emphasis) for each cell, of each signal transition state of an input/output terminal, and inter-cell wiring information are obtained as input information of a power consumption calculation process.
Then, power consumption is obtained based on a signal transition of an input/output terminal of each cell, and a calculation of signal propagation to a cell at a succeeding stage and a power calculation of a load capacitance are performed based on the wiring information. A total of power is obtained by executing such a power calculation process for transition information of all signals of all circuits within the integrated circuit, so that power consumption of the entire integrated circuit is calculated.
There is one example of related techniques in which, when the power consumption of an integrated circuit including a large-scale circuit block (mega cell) such as an SRAM (Static Random Access Memory) macro or the like included in an LSI is calculated, power consumption of each state of an input terminal of each mega cell is obtained, and the power consumption of the mega cell and results of a logic simulation process are combined to calculate the power consumption of the integrated circuit.
There is another example of the related techniques, in which power consumption of each transition operation of basic circuits (basic cells) such as an inverter circuit (NOT circuit), an AND circuit, a NAND circuit, an OR circuit, a NOR circuit and the like, are obtained in advance and the number of transition operations of the basic circuits with a logic simulation is obtained to calculate power consumption of the entire integrated circuit from the power consumption of each transition operation and the number of transition operations based on of parameters of a predetermined logic circuit.
There is a further example of the related techniques, in which holding power consumption information of a circuit is held, and power consumed when an output of the circuit does not change and power consumed when the output of the circuit changes are obtained to obtain power consumption of a basic circuit based on a coefficient corresponding to the number of changes of the output per unit time according to a change of an input when the input of the circuit changes.
However, the related techniques do not take into account accuracy assurance in a power consumption calculation even if circuit complexity increases with a growing scale of a cell. This leads to a problem that the accuracy of a power consumption calculation of a cell is degraded when the whole of a large-scale circuit is designed as a transistor. Namely, with conventional techniques, it is needed to simulate operations of transistors collectively for the entire cell. However, if the number of input/output terminals of the cell becomes very large as in a 64-bit adder, the number of all combinations of states of inputs/outputs of the cell becomes enormous, leading to a very long time needed for the simulation process. Therefore, it is difficult to actually calculate power consumption of each transition state of an input/output signal.
Furthermore, if the number of transistors within a cell increases, a time needed for a circuit simulation process (such as a SPICE simulation process) of each transition state of an input/output signal becomes further long. Therefore, it is impossible to actually calculate power consumption with the circuit logic simulation process.
Still further, for a cell including many circuits for holding an internal state such as a latch array including a plurality of latches, its internal operation differs depending on a discrepancy of a held internal state even in the same input signal transition. Therefore, power consumption of the cell cannot be properly obtained only based on a transition state of an input/output signal.
There is a technique of obtaining power consumption of each state for a mega cell as one related technique. However, this technique obtains power consumption not by classifying all states within the mega cell but by respectively classifying states according to typical operations such as functions or the like. Therefore, this technique cannot detect a difference of power consumption, which is caused by a discrepancy among details of states within the mega cell, leading to a decrease in the accuracy of the power consumption calculation.